`timescale 1ns/1ns
module mux4_to_1_tb;
	reg input_1,input_2,input_3,input_4;
	reg s1,s2;
	wire out;
	mux4_to_1 ul(.out(out),.input_1(input_1),.input_2(input_2),.input_3(input_3),.input_4(input_4),.s1(s1),.s2(s2)); 
	initial begin
		input_1 = 2'b01;
		input_2 = 2'b10;
		input_3 = 2'b01;
		input_4 = 2'b10;

		s2=0;s1=0;#100;
		s2=0;s1=1;#100;
		s2=1;s1=0;#100;
		s2=1;s1=1;#100;
	end
endmodule
